Many electronic systems such as computers are constructed from a plurality of chips that are interfaced to a synchronous bus. The transfer of data between the various chips and the bus is synchronized with a bus clock whose maximum speed is determined by the electrical characteristics of the bus.
In many cases, the chips are capable of running at significantly higher clock speeds than the bus can support. The internal speed of a chip is limited by the length of conductors in the chip and by the various parasitic capacitances in the chip. Since signal propagation distances in a chip are much smaller than the signal propagation distances on the bus, chips can often run at much higher speeds than the bus. If the chips do not need to transfer data to or from the bus on each bus cycle, a significant speed advantage may be obtained by running the chips at a clock speed that exceeds the bus clock.
Computer systems in which the microprocessor chip runs at a multiple of the bus speed are known to the prior art. For example, systems in which the microprocessor operates at a clock speed that is twice the bus speed are commercially available. Since a microprocessor may require several internal clock cycles to execute an instruction, running the microprocessor at a higher speed than the bus clock results in a significant reduction in the execution of such instructions.
Unfortunately, such microprocessor systems can only run at fixed integer multiples of the bus clock. The optimum ratio between the chip clock and the bus clock is determined by the system parameters. In a system having a very fast bus, the optimum ratio will be smaller than in a system having a slower bus. In prior art synchronous systems, such as the microprocessors discussed above, a different chip, or at least additional bus logic circuits, is needed to implement a few fixed ratios of chip speed to bus speed. The cost of providing a number of different chips is prohibitive; hence, the optimum ratio is seldom achieved.
Systems in which data is transferred asynchronously between the bus and chips avoid these problems, since the internal clock of a chip is free to operate at any speed relative to the bus speed. Unfortunately, these systems require much more complex bus interface hardware. In addition, the timing of the system operations can not always be predicted in asynchronous systems. Such timing uncertainties can lead to problems in multi-processor systems that rely on a predictable execution order for instructions.
Broadly, it is the object of the present invention to provide an improved method for synchronizing chips to a bus.
It is a further object of the present invention to provide a synchronous bus interface system that allows the chips to run at a plurality of different clock speeds for any given bus speed.
These and other objects of the present invention will become apparent to those skilled in the art from the following detailed description of the invention and the accompanying drawings.